1. Field of the Invention
The present invention relates to a barrel shifter in which the operating time can be greatly reduced and increase of the cell array area can be suppressed at the minimum value.
2. Description of the Background Art
Recently, a barrel shifter in which data composed of a binary code series are received in parallel and provided in parallel after shifted at will by a desired number of bits has been utilized for an arithmetical unit for LSI (Large Scale Integration).
FIG. 1 shows a block diagram of a cell array section of a conventional barrel shifter having i stages (i is an integer satisfying 1.ltoreq.i).
As shown in FIG. 1, in the barrel shifter composed of i stages, a plurality of selectors 1 are arranged in parallel correspondingly to each bit of an input data formed of a binary code series of D1, D2, . . . , further interconnected in series so as to construct i stages. To each of the selectors 1, a corresponding binary code and another binary code different from the former binary code by a predetermined bit number are received, and one of these two codes is selected and provided in such a manner as described later. For example, a k-bit-shifting (k is an optional integer and satisfies 1.ltoreq.k) control signal for the m-th stage, an inverted-k-bit-shifting control signal obtained by inverting the k-bit-shifting signal, a reference code from a selector 1 of the (m+1)th stage located just above the selector 1 of the m-th stage in FIG. 1 and a binary code (k-bit-shifted code) different from the reference code by k bits and given from a selector 1 which is located at the k-th position in the right direction from the selector 1 of the (m+1)th stage in FIG. 1 and provides the reference code, are received to a selector 1 of the m-th (1.ltoreq.m.ltoreq.i) stage.
Moreover, the selector 1 of the m-th stage provides a binary code selected by its operation to a selector 1 of the (m-1)th stage located just below in FIG. 1 and a selector 1 located at the j-th position (j is an optional number and satisfies 1.ltoreq.j) in the left direction from the selector 1 of the (m-1)th stage in FIG. 1.
To each of selectors 1 of the i-th stage located at the top stage in FIG. 1, a corresponding binary code, that is, a reference code and another binary code different from the reference code by n bits, that is, an n-bit-shifted code are selectively received from the binary code series of D1, D2, . . . .
On the other hand, a binary code series of OUT1, OUT2, . . . , provided from respective selectors 1 of the first stage located at the bottom stage in FIG. 1, composes an output data.
For example, as shown in FIG. 2, the selector 1 of the m-th stage is composed of a transfer gate in which two N channel MOS type FET transistors (hereinafter called Nch) 2, 3 are connected in parallel. And the k-bit-shifted code is received to a source of the Nch2, while the k-bit-shifting control signal is received to a gate of the Nch2. On the other hand, the reference code is received to a source of the Nch3, while the inverted-k-bit-shifting control signal is received to a gate of the Nch3.
In such construction of the selector 1, when the k-bit-shifting control signal is at the "H" level (for example, at a positive power-source potential), only a channel between the source and the drain of the Nch 2 to which the signal is received is turned on, so that the k-bit-shifted code is provided. To the contrary, when the k-bit-shifting control signal is at the "L" level (for example, 0 potential), since the inverted-k-bit-shifting control signal is at the "H" level, only a channel between the source and the drain of the Nch 3 to which the inverted signal is received is turned on, so that the reference code is provided.
Namely, the selector 1 selects and provides the k-bit-shifted code or the reference code under control of the k-bit-shifting control signal.
Returning to FIG. 1, the operation of a barrel shifter in which the selectors 1 operated in the above manner are respectively arrayed in series so as to construct i stages is explained.
Each of selectors 1 of the i-th stage located at the top stage receives the reference code and the n-bit-shifted code which is different from the reference code by n bits in the binary code series of D1, D2, . . . .
In other words, the group of selectors 1 of the i-th stage receives a reference data composed of the binary code series of D1, D2, . . . and a n-bit-shifted data which is shifted by n bits from the reference data.
Then, each selector 1 of the i-th stage selects the reference code or the n-bit-shifted code under control of the n-bit-shifting control signal or the inverted-n-bit-shifting control signal.
In other words, since all of the selectors 1 of the i-th stage receive the same n-bit-shifting control signal and the same inverted-n-bit-shifting control signal, the group of selectors 1 selects either the reference data or the n-bit-shifted data.
Then, each selector 1 of the i-th stage provides each selected binary code to each selector 1 of the (i-1)th stage located just below in FIG. 1 and each of another selectors 1 located at the h-th position (h is an optional integer satisfying 1.ltoreq.h) in the left direction from the former selector 1 of the (i-1)th stage in FIG. 1.
Namely, each of the selectors 1 of the (i-1)th stage receives the binary code selected and provided from the selector 1 in the i-th stage just above in FIG. 1 as a new reference code and another binary code provided from a selector 1 of the i-th stage located at the h-th position in the right direction from the former selector 1 of the i-th stage in FIG. 1 as an h-bit-shifted code which is shifted from the reference code by h bits.
In other words, the group of selectors 1 of the i-th stage provides a data selected by its operation as a new reference data and an h-bit-shifted data respectively shifted by h bits from the new reference data to the group of selectors 1 of the (i-1)th stage.
In such a manner, each selector 1 of each stage selects either the received reference code or the k-bit-shifted code under control of the k-bit-shifted control signal and the inverted k-bit-shifted control signal, and provides the selected binary code as a new reference code to a selector 1 in the following stage and provides the same code as a j-bit-shifted code to another different selector from the former selector in the same following stage.
In other words, each group of selectors 1 of each stage selects either the reference data or the shifted data shifted by an optional number of bits from the reference data, and provides the selected data and the shifted data shifted by an optional number of bits from the selected data to the following stage one after another. Moreover, the group of selectors 1 of the bottom stage provides the selected data composed of the binary code series of OUT1, OUT2, . . . as an output data.
The output data coincides with the data obtained by shifting the input data composed of the binary code series of D1, D2, . . . by the total bit number defined by summing up each predetermined bit number shifted by every group of the selectors 1 in each stage.
Accordingly, by using the above-mentioned construction in which the selectors 1 respectively composed of transfer gates of Nch are arranged in order in a matrix form, it becomes possible to form a barrel shifter having a compact shape and it is capable of shifting a data by a desired number of bits.
As shown in FIG. 3, it is possible to use a pass transistor as each selector 1 in place of the transfer gate shown in FIG. 2. Namely, in such a pass transistor, P channel MOS type FET transistors (called Pch hereinafter) 4, 5 are respectively connected in parallel with the Nch 2, 3 to compose circuits 6, 7 which are connected in parallel to each other.
In this case, since the pass transistor has the Pch in which the so-called back gate effect is not generated, when a binary code received to the selector 1 is at the "H" level (for example, a power-source potential), the electric potential of a code to be provided therefrom reaches the power-source potential so that the binary code can be transmitted rapidly and reliably.
However, in such a barrel shifter as composed of selectors each of which uses the transfer gate or the pass transistor, when the number of stages of the selectors arranged in series is increased, the distortion of output codes becomes remarkable. As a result, the operating time of the barrel shifter is greatly increased and the processing speed of the input data is declined.
For example, FIG. 4a shows input/output waveforms when an edge signal is received from a pass transistor of the sixth stage in a barrel shifter composed of six stages.
As shown in FIG. 4b, the horizontal axis shows the elapsed time (nsec), and the vertical axis shows the voltage (volt) of output signals obtained in each stage. Moreover, a signal e1 designates an input edge signal, a signal e2 designates a signal provided from the pass transistor of the sixth stage in which the signal e1 is received. In other words the signal e2 designates an input signal to a pass transistor of the fifth stage. Similarly, a signal e3 designates an output signal from the pass transistor of the fifth stage. In other words, the signal e3 designates an input signal to a pass transistor of the fourth stage, and e4 designates an output signal from a pass transistor of the third stage. In other words, the signal e4 designates an input signal to a pass transistor of the second stage, moreover a signal e5 designates an output signal from a pass transistor of the first stage which is the final stage of the barrel shifter.
Each of the Nch has a channel length of 1 .mu.m and a channel width of 3 .mu.m, While each of the Pch has a channel length of 1 .mu.m and a channel width of 5 .mu.m. Moreover, the power source voltage is 4.5 volt.
As shown in FIG. 4b, the signal e1 rises up sharp. However, it is also seen from the same drawing that the each waveform of the signals is gradually distorted every time the signal passing through each stage.
For example, as the logic criteria in this case, when the voltage set in the range from 0 to 2.5 volt is an "L" level, while the voltage set in the range from 2.5 to 4.5 volt is an "H" level, the input signal e1 which starts to rise up at t0=15 nsec exceeds the voltage of 2.5 volt at t1=17 nsec, while the output signal e5 exceeds the voltage of 2.5 volt at t5=26 nsec. Accordingly, the operating time in the six stages of selectors is obtained as 9 nsec defined by the value of t5-t1.
The reason why each signal waveform rises relatively sharp in the vicinity of 2.4 volt is because the Pch cause no back gate effect.
Moreover, the reason why the waveform is gradually distorted is that each of the transistors respectively forming the selectors has an internal resistance, an internal electrostatic capacitance and a wiring capacitance. Hereinafter, the influence of the resistance and the capacitance is explained in detail with reference to FIGS. 5a and 5b.
FIG. 5a is an explanatory diagram to show a transmission route of a shifted data when the barrel shifter is composed of selectors using the pass transistors. For convenience, the same drawing shows a circuit in which only the circuits 7 in the circuits 6, 7 composing the series of selectors are connected in series.
As shown in FIG. 5a, in the circuit connecting selectors in series, shifting control signals S1, S2, . . . are respectively received to the gates of Pch 5, and the inverted signals IS1, IS2, . . . obtained by inverting the control signals are respectively received to the gates of Nch 3. In such a state, the binary code D1 is received to a source of a pair of Nch-Pch of the top stage in FIG. 5a, then the binary code OUT1 is provided from a drain of the pair of Nch-Pch of the bottom stage in FIG. 5a.
From the viewpoint of the internal resistance, the internal electrostatic capacitance and the wiring capacitance, the circuit connecting selectors in series can be regarded as a circuit composed of RC circuits connected in series with each other as shown in FIG. 5b.
Accordingly, when the number of stages composed of selectors is increased, the delay time caused by the respective RC circuits is increased, so that the distortion of the output code OUT1 becomes considerably large.
The improvement to optimize the size of the transistor and reduce the delay time has been tried. However, when the signal of the "H" level is transmitted rapidly, it is necessary to enlarge the size of the Pch transistor reasonably. Accordingly, though the optimization of size is possible to some extent, it is necessary to increase the area of the barrel shifter drastically on the whole.
Moreover, to avoid the distortion of the binary code transmitted through the stages of the selectors, there is a known method in which for example, two stages of drivers 8 are inserted in the series of stages as shown in FIG. 6 to shape the waveform of the binary code.
However, when this method is used, since the layout area of the drivers 8 is required in the cell array section of the barrel shifter the method is inconsistent with reality.